Integration of III-V Nanowire Semiconductors for next
Generation High Performance CMOS SOC TECHNOLOGIES

News archive

The INSIGHT project will be extended

Published: 2018-09-07

The EC has, upon the request of the consortium, decided to extend the duration of the INSIGHT project for an additional 6 months, thus postponing the end of the project into 2019 (31 May 2019). This will give the team time to do the most out of the technology development that has been achieved thus far, and demonstrate the full potential of the III-V nanowire device technology platforms for digital and millimeter wave applications.


IBM and IAF presents highlight talk at VLSI 2018

Published: 2018-09-07

The IBM and Fraunhofer IAF team presented their work titled InGaAs-on-Insulator "MOSFETs Featuring Scaled Logic Devices and Record RF performance" at the 2018 VLSI Symposium in Honolulu, Hawaii, USA. The paper was selected as a highlight of the conference, a true appreciation of the fantastic work of the team!

Below follows the abstract of the paper:

We demonstrate scaled InGaAs-on-insulator FinFETs and
planar MOSFETs on Si substrate for low power logic and RF
applications. This Si-CMOS compatible technology
implements SiNx source-drain spacers and doped extensions
for reduced overlap capacitances. FinFETs with performance
for logic applications matching state-of-the-art are
demonstrated. Simultaneously, ft and fmax of 400 and 100 GHz
are achieved respectively, the highest reported ft for a III-V
MOSFET on Si. Finally, we explore the use of an extended
gate line to reduce gate resistance, offering balanced ft/fmax of
215/300 GHz, the first report of III-V RF devices on Si
matching state of the art Si-CMOS.


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