INSIGHT

Integration of III-V Nanowire Semiconductors for next
Generation High Performance CMOS SOC TECHNOLOGIES

News archive, 2016

INSIGHT participates in Joint Scientific Workshop at ESSDERC

Published: 2016-12-18

To advance the collaboration between INSIGHT and other important consortia in the European III-V semiconductor research field, we have participated in a joint Scientific Workshop arranged by III-V MOS and Compose3 at the ESSDERC-ESSCIRC'2016 conference in Lausanne, Switzerland. 

The workshop was held on September 12th and was titled "III-V compound semiconductor technology and devices for advanced nanoelectronics".

The workshop was a privileged forum to hear leading industrial and academic experts illustrate the state-of-the-art and attempt answering the following questions:

  • How far ahead is the III-V/SiGe scenario, and what are the remaining technological roadblocks?
  • Are TCAD and compact models for III-V devices on Silicon ready to support the circuit design?
  • What devices, circuits and applications will benefit most of III-V/SiGe integration?

An open atmosphere for discussion fostered the exchange of ideas and the sharing of personal views during the workshop. It also set the foundation for further scientific collaboration between the INSIGHT partners and members of the other two consortia.



 


The Consortium ambition

Published: 2016-05-03

The INSIGHT consortium partners state their ambition and INSIGHT potential during their 1st Consortium Meeting in Glasgow in April 2016



 


INSIGHT Press release 2016

Published: 2016-03-02

INSIGHT: Meeting the increasing performance demands at millimetre-wave frequencies

Future radar imaging systems and 5G communication systems will generate improved resolution and provide higher data-transmission rates when operated at higher frequencies, but at the cost of increased power consumption. To reduce power consumption, increase performance, and lower costs, the European project INSIGHT (Integration of III-V Nanowire Semiconductors for Next Generation High Performance CMOS SOC Technologies) is aiming at developing III-V CMOS (complementary metal-oxide-semiconductor) technology. The six partners, including universities, research institutes and one company, are committed to establishing a manufacturable III-V CMOS technology on Si substrates, to reduce costs and to save scarce materials.

The INSIGHT mission is to develop complementary functionality in compound semiconductor material (III-V CMOS), supporting both analogue and digital functionality in the millimetre-wave frequency domain. III-V nanowires will be used to maintain electrostatic control, as the gate length is scaled for future technology nodes. The small nanowire cross-section further facilitates the integration onto Si substrates using nanotechnology. “The fabrication of high-performance III-V components on large Si substrates using CMOS compatible technologies opens a path for cost reduction of millimetre-wave key components with minimized usage of critical materials” says Lars-Erik Wernersson, Professor at Lund University and coordinator for INSIGHT. Lund University is coordinating this new European Horizon 2020 research project that has been funded with 4.3 million Euros over 36 months.

IBM foresees a growing need to push the limits of chip technology to meet the emerging demands of cognitive computers, Internet of Things and Cloud platforms, due to the enormous amount of data they are handling – 90% of which is unstructured. The new technology developed in INSIGHT offers a potential solution to scale chip technology beyond the 10 nm node as well as opening up a range of new application areas. Integrating III-V materials into Si CMOS can enable better logic circuits with a lower power consumption, and in addition can enable the realization of System-on-Chip (SoC) products taking full advantage of III-V's state-of-the-art RF/Analog metrics.

There is a growing need for performance enhancements of key components in the millimetre-wave frequency range and new consumer applications are demanding low costs. The new technology offers a potential solution, as it may provide both high-performance analogue and digital functionality on the same platform where the improved manufacturability allows production on larger wafers. The INSIGHT consortium addresses the technology need with the ambition to demonstrate circuits and systems by optimizing both material and device properties.

The introduction of III-V materials on silicon substrates by using nanowires is one of the most innovative heterogeneous integration approaches today. Fraunhofer IAF will bring in their III-V process and circuit design experience, and is interested in transferring the results and findings to next generation III-V device technologies.

The LETI participation in the INSIGHT project involves both the Silicon Component division and the Integrated Circuit & Embedded System division, ranging from materials to the circuit demonstration. The technology expands the LETI platform for smart devices and Internet of Things with the potential to squeeze multiple functions into a single die.

III-V CMOS technology may be particularly suited for millimetre-wave front-ends where it will be used to detect and generate signals for communication, radar and imaging. It is the goal of the INSIGHT consortium to develop key technologies for both the receivers and transmitters, while exploring the limits of the transistor geometry and layout.

Besides Fraunhofer IAF (Germany) and LETI (France), the consortium consists of Lund University (Sweden), University of Glasgow (UK), Tyndall National Institute (Ireland) and IBM (Switzerland). The expertise of the partners spans the complete spectrum from materials, through devices, all the way to circuits and systems, allowing the consortium to take this promising technology further along the path to commercial products. INSIGHT is funded under the Horizon 2020 Programme for Research and Development of the European Union (Grant agreement number 688784).



 


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